The present invention relates to a method of manufacturing a transistor array.
Generally, a thin film transistor (to be abbreviated as TFT hereinafter) is known as a transistor. TFTs are widely used as switching elements of active drive liquid crystal display devices. One of the conventionally known methods of manufacturing TFT arrays is illustrated in FIGS. 17 to 25. This method is designed for manufacturing a TFT of a reverse stagger type. First, FIG. 17 shows a state in which a gate electrode 202 made of aluminum, and a gate pad portion 203 serving as a terminal portion of a gate line connected to the gate electrode 202 are formed on the surface of a glass substrate 201 by patterning. After this, a resist 204 is formed only in a contact region 203A of the upper surface of the gate pad 203 by patterning. The resist 204 is patterned such that it is placed on the contact region 203A of the upper surface, so that a peripheral portion of the upper surface of the gate pad portion 203 is exposed. Then, an oxidizing treatment is carried out to from an anodic oxidized film 205 on the exposed surface of the Al film of the gate electrode 202, and an anodic oxidized film 206 on a circumferential side of the gate pad portion 203 and on the periphery of the upper surface thereof, respectively, as shown in FIG. 18. After that, as can be seen in FIG. 19, a gate insulation film 207 made of, for example, silicon nitride, a silicon film 208 made of amorphous silicon and a silicon nitride film 209 are respectively formed in the order. Subsequently, a resist mask 210 is formed on the silicon nitride film 209 located above the gate electrode 202. Then, the silicon nitride film 209 is selectively etched by wet-etching using buffered hydrofluoric acid to form a blocking layer 209A in the section corresponding to that of the silicon film 208 located above the gate electrode 202. After that, the resist 210 is removed.
Subsequently, for example, n.sup.+ -type amorphous silicon film doped with an impurity, is deposited on the blocking layer 209A and the silicon film 208. Then, as shown in FIG. 20, a selective etching is carried out such that the n.sup.+ -type amorphous silicon film is separated on the blocking layer 209A into a drain side and source side, thus forming impurity semiconductor islands 211A and 211B. Further, the silicon film 208 is selectively etched so as to form a semiconductor island 208A. Then, as can be seen in FIG. 21, a pixel electrode 212 made of ITO (indium tin oxide) is formed on the gate insulating film 207 by the patterning method which uses a resist mask 220. In the patterning of ITO, a wet etching technique is employed with use of a hydrochloric acid-based etching solution. Further, as shown in FIG. 22, after a resist mask 213 having a contact hole 213A is formed, an etching is performed so as to form a contact hole 207A in the gate insulation film 207 on the upper surface of the gate pad portion 203. Thus, the contact region of the gate pad 203 is exposed.
Next, the resist mask 213 is removed, and then a source-drain metal film is deposited on the entire surface. After that, a resist mask having a predetermined pattern (not shown) is formed on the metal film, and with use of this resist mask as a mask, the source-drain metal film is patterned, thus forming a source electrode 215, a drain electrode 214 and a gate pad metal film 216 as shown in FIG. 23. Then, as shown in FIG. 24, an overcoat film 217 made of, for example, silicon nitride, is formed thereon, thus completing the manufacturing process of the conventional TFT.
In such a conventional TFT array, terminal portions (pad portions) for connecting the gate line and the drain line to external circuits. Some of the examples of the etching solution for silicon nitride which makes the blocking layer 209A, are buffered hydrofluoric acid and hot phosphoric acid, which have a property of easily corroding aluminum or aluminum alloy. In the step of wet-etching the silicon nitride film 209 shown in FIG. 19, a pin hole 218 can be easily made in the backing silicon film 208, as an enlarged view of which is shown in FIG. 25. Therefore, when a pin hole is actually created, and the silicon film 208 is made very thin (for example, less than 1,000 angstrom), the etching solution reaches the gate insulation film 207 made of silicon nitride. As a result, a pin hole can be easily made also in the gate insulation film 207. Since the contact region 203A made on the upper surface of the gate pad portion 203 is not protected by the anodic oxidized film 4, unlike the case of the gate line or the gate electrode portion, if such a pin hole is made in the film 207, the etching solution reaches the gate pad portion 203 through the hole, so as to easily corrode it. Thus, as shown in FIG. 25, a cavity 219 is made in the gate pad portion 203, or in worse cases, the disconnection of the wiring occurs.
Further, in the step shown in FIG. 21, which is carried out after the step shown in FIG. 19, the ITO film, which gives rise to the pixel electrode 212, is etched with a hydrochloric acid-based etching solution. However, there is nothing but the gate insulation film 207 formed on the contact region 203A, and therefore, if a pin hole is made in the gate insulation film 207 as described above, the hydrochloric acid-based etching solution corrodes Al of the gate pad portion 203, which raises a problem. Especially, in the case of a metal film containing Al, projections so-called "hillock" are occasionally created when the film is heated at about 250.degree. C. Consequently, a defect occurs more easily in the portion of the gate insulation film 207, which covers such a projecting section, than in other sections. Although the occurrence rate of film defects themselves, including the creation of a pin hole, is low, the yield of production is lowered in the case of liquid crystal display devices each having a TFT array of a finely integrated wiring structure.